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CENTRALE LYON - Post-Doctoral Position Ferroelectric-Based Ternary Computing: From Circuit Design to System-Level Integration Scientific Context
CENTRALE LYON
Contract type
Ongoing
Work mode
Remote · France
Experience
3 years
Job description
Post-doctoral position at Centrale Lyon / INL on in-memory computing with ferroelectric FeFET devices, covering standard-cell library design, ternary arithmetic units, system-level modeling, and hardware/software co-design.
At a glance
- Work mode
- Remote · France
- Languages
- English – fluent, French
What you'll do
- Design a standard cell technology library based on FeFET devices developed at INL for use with synthesis flow
- Design and optimize ternary arithmetic units (multiply-accumulate units, adders, comparators) based on the FeFET ternary gate library, targeting area, power, and timing closure under realistic process constraints
- Develop and refine system-level models of FeFET-based ternary IMC units, abstracting circuit-level characterization results into architecture simulators for design space exploration
- Investigate hardware/software co-design strategies for mapping applications such as CNNs and signal processing kernels onto the ternary IMC fabric, exploiting approximate computing
- Assess and benchmark energy, performance, and accuracy trade-offs of ternary IMC against binary CMOS and binary NVM-based IMC reference implementations
- Contribute to the definition of a design methodology for ternary ferroelectric circuits, including EDA tool flows, cell library characterization guidelines, and design rules
What we're looking for
- PhD in microelectronics, computer architecture, or a closely related field
- At least one of: strong expertise in digital circuit design flows and computer architecture with hands-on experience using industrial EDA tools (Cadence Virtuoso/Spectre, Synopsys); solid knowledge of non-volatile memory devices, preferably ferroelectric materials (FeFET, FeCap) or resistive memories (RRAM, PCM); experience with architecture-level simulation frameworks and hardware/software co-des
- Proficiency in HDL (Verilog, VHDL, Verilog-A) and scripting languages (Python, Shell) for design automation and simulation
- Scientific leadership, ability to coordinate with PhD students and international partners, strong publication record consistent with career stage, and excellent written and oral communication in English
- Fluent scientific English is mandatory
Nice to have
- Experience with standard-cell library characterization
- Familiarity with compact modeling
- Knowledge of RISC-V ecosystems
- French is welcome but not required
Your team
INL
FeFET devices developed at INL